@zwh8800
2017-08-23T02:07:15.000000Z
字数 8262
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blog 归档 ARM
ARM 核和 ARM 指令集大致是这样对应
ARM7TDMI ARMv4T
ARM9E ARMv5TE
ARM11 ARMV6
cortex ARMv7
下面是网上找的乱七八糟的列表 将就着看 反正 cortex 以前的都是老黄历了 唉
ARM7TDMI
v4T
ARM7TDMI-S
v4T
ARM7EJ-S
v5E
DSP,Jazelle
[译注 3]
ARM920T
v4T
MMU
ARM922T
v4T
MMU
ARM926EJ-S
v5E
MMU
DSP,Jazelle
ARM946E-S
v5E
MPU
DSP
ARM966E-S
v5E
DSP
ARM968E-S
v5E
DMA,DSP
ARM966HS
v5E
MPU（可选）
DSP
ARM1020E
v5E
MMU
DSP
ARM1022E
v5E
MMU
DSP
ARM1026EJ-S
v5E
MMU 或 MPU
[译注 2]
DSP, Jazelle
ARM1136J(F)-S
v6
MMU
DSP, Jazelle
ARM1176JZ(F)-S
v6
MMU+TrustZone
DSP, Jazelle
ARM11 MPCore
v6
MMU + 多处理器缓存支持
DSP
ARM1156T2(F)-S
v6
MPU
DSP
Cortex-M3
v7-M
MPU（可选）
NVIC
Cortex-R4
v7-R
MPU
DSP
Cortex-R4F
v7-R
MPU
DSP + 浮点运算
Cortex-A8
v7-A
MMU+TrustZone
DSP, Jazelle
［译注 2］：Jazelle 是 ARM 处理器的硬件 Java 加速器。
［译注 3］：MMU，存储器管理单元，用于实现虚拟内存和内存的分区保护，这是应用处理器与嵌入式处理器的分水岭。电脑和数码产品所使用的处理器几乎清一色地都带 MMU。但是 MMU 也引入了不确定性，这有时是嵌入式领域——尤其是实时系统不可接受的。然而对于安全关键（safety-critical）的嵌入式系统，还是不能没有内存的分区保护的。为解决矛盾，于是就有了 MPU。可以把 MPU 认为是 MMU 的功能子集，它只支持分区保护，不支持具有 “定位决定性” 的虚拟内存机制。
到了架构 7 时代，ARM 改革了一度使用的，冗长的、需要 “解码” 的数字命名法，转到另一种看起来比较整齐的命名法。比如，ARMv7 的三个款式都以 Cortex 作为主名。这不仅更加澄清并且 “精装” 了所使用的 ARM 架构，也避免了新手对架构号和系列号的混淆。例如，ARM7TDMI 并不是一款 ARMv7 的产品，而是辉煌起点——v4T 架构的产品。
———————–update—————————-
补个表格 from wikipedia
| ARM Family | ARM Architecture | ARM Core | Feature | Cache (I / D), MMU | Typical MIPS @ MHz |
|---|---|---|---|---|---|
| ARM1 | ARMv1 | ARM1 | First implementation | None | |
| ARM2 | ARMv2 | ARM2 | ARMv2 added the MUL (multiply) instruction | None | 4 MIPS @ 8 MHz
0.33 DMIPS/MHz |
| ARMv2a | ARM250 | Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions. | None, MEMC1a | 7 MIPS @ 12 MHz | |
| ARM3 | ARMv2a | ARM3 | First integrated memory cache. | 4 KB unified | 12 MIPS @ 25 MHz
0.50 DMIPS/MHz |
| ARM6 | ARMv3 | ARM60 | ARMv3 first to support 32-bit memory address space (previously 26-bit) | None | 10 MIPS @ 12 MHz |
| ARM600 | As ARM60, cache and coprocessor bus (for FPA10 floating-point unit). | 4 KB unified | 28 MIPS @ 33 MHz | ||
| ARM610 | As ARM60, cache, no coprocessor bus. | 4 KB unified | 17 MIPS @ 20 MHz
0.65 DMIPS/MHz |
||
| ARM7 | ARMv3 | ARM700 | 8 KB unified | 40 MHz | |
| ARM710 | As ARM700, no coprocessor bus. | 8 KB unified | 40 MHz | ||
| ARM710a | As ARM710 | 8 KB unified | 40 MHz
0.68 DMIPS/MHz |
||
| ARM7TDMI | ARMv4T | ARM7TDMI(-S) | 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing | none | 15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz |
| ARM710T | As ARM7TDMI, cache | 8 KB unified, MMU | 36 MIPS @ 40 MHz | ||
| ARM720T | As ARM7TDMI, cache | 8 KB unified, MMU with Fast Context Switch Extension | 60 MIPS @ 59.8 MHz | ||
| ARM740T | As ARM7TDMI, cache | MPU | |||
| ARM7EJ | ARMv5TEJ | ARM7EJ-S | 5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions | none | |
| ARM8 | ARMv4 | ARM810[4][5] | 5-stage pipeline, static branch prediction, double-bandwidth memory | 8 KB unified, MMU | 84 MIPS @ 72 MHz
1.16 DMIPS/MHz |
| ARM9TDMI | ARMv4T | ARM9TDMI | 5-stage pipeline, Thumb | none | |
| ARM920T | As ARM9TDMI, cache | 16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)[6] | 200 MIPS @ 180 MHz | ||
| ARM922T | As ARM9TDMI, caches | 8 KB / 8 KB, MMU | |||
| ARM940T | As ARM9TDMI, caches | 4 KB / 4 KB, MPU | |||
| ARM9E | ARMv5TE | ARM946E-S | Thumb, Enhanced DSP instructions, caches | variable, tightly coupled memories, MPU | |
| ARM966E-S | Thumb, Enhanced DSP instructions | no cache, TCMs | |||
| ARM968E-S | As ARM966E-S | no cache, TCMs | |||
| ARMv5TEJ | ARM926EJ-S | Thumb, Jazelle DBX, Enhanced DSP instructions | variable, TCMs, MMU | 220 MIPS @ 200 MHz | |
| ARMv5TE | ARM996HS | Clockless processor, as ARM966E-S | no caches, TCMs, MPU | ||
| ARM10E | ARMv5TE | ARM1020E | 6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP) | 32 KB / 32 KB, MMU | |
| ARM1022E | As ARM1020E | 16 KB / 16 KB, MMU | |||
| ARMv5TEJ | ARM1026EJ-S | Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP) | variable, MMU or MPU | ||
| ARM11 | ARMv6 | ARM1136J(F)-S[7] | 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions | variable, MMU | 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz |
| ARMv6T2 | ARM1156T2(F)-S | 8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions | variable, MPU | ||
| ARMv6Z | ARM1176JZ(F)-S | As ARM1136EJ(F)-S | variable, MMU + TrustZone | 965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors[8] | |
| ARMv6K | ARM11 MPCore | As ARM1136EJ(F)-S, 1–4 core SMP | variable, MMU | ||
| SecurCore | ARMv6-M | SC000 | 0.9 DMIPS/MHz | ||
| ARMv4T | SC100 | ||||
| ARMv7-M | SC300 | 1.25 DMIPS/MHz | |||
| Cortex-M | ARMv6-M | Cortex-M0 [9] | Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory | No cache, No TCM, No MPU | 0.84 DMIPS/MHz |
| Cortex-M0+ [11] | Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory | No cache, No TCM, optional MPU with 8 regions | 0.93 DMIPS/MHz | ||
| Cortex-M1 [12] | Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory | No cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, No MPU | 136 DMIPS @ 170 MHz,[13] (0.8 DMIPS/MHz FPGA-dependent)[14] | ||
| ARMv7-M | Cortex-M3 [15] | Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory | No cache, No TCM, optional MPU with 8 regions | 1.25 DMIPS/MHz | |
| ARMv7E-M | Cortex-M4 [16] | Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory | No cache, No TCM, optional MPU with 8 regions | 1.25 DMIPS/MHz | |
| Cortex-R | ARMv7-R | Cortex-R4 [17] | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic | 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 8/12 regions | |
| Cortex-R5 (MPCore) [18] | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) [19] | 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt MPU with 12/16 regions | |||
| Cortex-R7 (MPCore) [20] | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP [19] | 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt MPU with 16 regions | |||
| Cortex-A | ARMv7-A | Cortex-A5 [21] | Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) | 4-64 KB / 4-64 KB L1, MMU + TrustZone | 1.57 DMIPS / MHz per core |
| Cortex-A7 MPCore [22] | Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design[23] | 32 KB / 32 KB L1, 0–4 MB L2, MMU + TrustZone | 1.9 DMIPS / MHz per core | ||
| Cortex-A8 [24] | Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline | 16-32 KB / 16–32 KB L1, 0–1 MB L2 opt ECC, MMU + TrustZone | up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz) | ||
| Cortex-A9 MPCore [25] | Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) | 16–64 KB / 16–64 KB L1, 0–8 MB L2 opt parity, MMU + TrustZone | 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core) | ||
| ARM Cortex-A12 [26] | Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) | 32-64 KB / 32 KB L1, 256 KB-8 MB L2 | 3.0 DMIPS / MHz per core | ||
| Cortex-A15 MPCore [27] | Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Integer divide / Fused MAC / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[23] | 32 KB Iw/parity / 32 KB D w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZone | At least 3.5 DMIPS/MHz per core (Up to 4.01 DMIPS/MHz depending on implementation).[28] | ||
| Cortex-A50 | ARMv8-A | Cortex-A53[29] | Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline | 8-64 KB w/parity / 8-64 KB w/ECC L1 per core, 128 KB-2 MB L2 shared, 40-bit physical addresses | 2.3 DMIPS/MHz |
| Cortex-A57[30] | Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline | 48 KB w/DED parity / 32 KB w/ECC L1 per core, 512 KB-2 MB L2 shared, 44-bit physical addresses | At least 4.1 DMIPS/MHz per core (Up to 4.76 DMIPS/MHz depending on implementation). | ||
| ARM Family | ARM Architecture | ARM Core | Feature | Cache (I / D), MMU | Typical MIPS @ MHz |