EEE339 Final Exam

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EEE339 2014-15

Question 2

module q2(A, B, C, D, S1, S2, OUT);
    input A, B, C, D, S1, S2;
    output OUT;
    wire w1, w2, w3, w4;
    assign w1 = A & B & S1;
    assign w2 = ~(S1 | C);
    assign w3 = ~(S2 ^ B ^ S1);
    assign w4 = ~(S1 & s2 & D);
    assign OUT = w1 | w2 | w3 | w4;
endmodule

Question 3

Asynchronous

module ff(clk, reset, out);
    input clk, reset;
    outout reg out;
    integer i = 0;
    initial
        out = 0;
    always@(posedge clk or negedge reset)
    begin
        if (reset) begin
            i = 0;
            out = 0;
        end
        else begin
            if (i >= 250) begin
                out = 1;
                i = 0;
            end
            else
                i = i + 1;
        end
    end
endmodule

Synchronous

module ff(clk, reset, out);
    input clk, reset;
    outout reg out;
    integer i = 0;
    initial
        out = 0;
    always@(posedge clk)
    begin
        if (reset) begin
            i = 0;
            out = 0;
        end
        else begin
            if (i >= 250) begin
                out = 1;
                i = 0;
            end
            else
                i = i + 1;
        end
    end
endmodule

Question 4

Mealy

module mealy(clk, reset, x, z);
    input clk, reset, x;
    output reg z;
    integer y, Y;
    parameter [2:0] S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;
    always @(x, y)
    begin
        case (y)
            S0: begin
                if (x) begin
                    z = 0;
                    Y = S1;
                end
                else begin
                    z = 0;
                    Y = S0;
                end
            end
            S1: begin
                if (x) begin
                    z = 0;
                    Y = S2;
                end
                else begin
                    z = 0;
                    Y = S0;
                end
            end
            S2: begin
                if (x) begin
                    z = 0;
                    Y = S3;
                end
                else begin
                    z = 0;
                    Y = S0;
                end
            end
            S3: begin
                if (x) begin
                    z = 1;
                    Y = S4;
                end
                else begin
                    z = 0;
                    Y = S0;
                end
            end
            S4: begin
                if (x) begin
                    z = 1;
                    Y = S4;
                end
                else begin
                    z = 0;
                    Y = S0;
                end
            end
        endcase
    end
    always @(posedge clk)
    begin
        if (reset == 1) y <= S0;
        else y <= Y;
    end
endmodule

Question 5

(a)

A 32%, B 27%, C 41%
Avg. CPI = 1.1*0.32 + 2.7*0.27 + 1.9*0.41
         = 1.86

A 29%, B 17%, C 54%
Avg. CPI = 1.1*0.29 + 2.7*0.17 + 1.9*0.54
         = 1.804

(b)

CPU Time = Instruction Count x CPI / Clock Rate

P1 CPU Time = 100 * 1.86  / 2800000000
P2 CPU Time = 100 * 1.804 / 2800000000

P1 / P2 = 1.86 / 1.804 = 1.031

Ans: P2 is 1.031 times faster than P2

Question 6

(a) Forwarding (in a pipeline)

Part 2 Lecture 13

(b) PC-relative addressing

Part 2 Lecture 5

(c) Single-cycle datapath

(d) Pipelining

Part 2 Lecture 12

(e) Exception

Part 2 Lecture 10-11 Page 21

Question 8

module CPU (clock, reset);
    parameter R_Type = 6'b0, LW = 6'b100011, SW = 6'b101011, BEQ = 6'b000100, J = 6'd2
    input clock, reset; // external inputs
    reg [31:0] PC, Regs[0:31], Memory [0:31], IR, ALUOut, MDR, A, B;
    reg [2:0] state; // processor state
    wire [5:0]] opcode;
    wire [31:0] SignExtend, PCOffset;
    assign opcode = IR[31:26]; // opcode is upper 6 bits
    assign SignExtend = {16{IR[15]}, IR[15:0]};
    assign PCOffset = SignExtend << 2; // PC offset is shifted
    // set the PC to 0 and start the control in state 1
    initial begin
        PC = 0;
        state = 1;
    end

    always @(posedge clock or posedge reset) begin
        Regs[0] = 0; // make sure R0 is always 0

        if (reset) begin
            PC = 0;
            state = 1;
            // words 0-15  used for instruction memory
            // words 16-31 used for data memory
            Memory[16] = 32'h5;
            Memory[17] = 32'hB;
        end

        case (state) // action depends on the state
            1: begin // first step: fetch the instruction, increment PC, go to next state
                IR <= Memory[PC>>2];
                PC <= PC + 4;
                state = 2; // next state
            end

            2: begin // second step
                A <= Regs[IR[25:21]];
                B <= Regs[IR[20:16]];
                ALUOut <= PC + PCOffset;
                state = 3;
            end

            3: begin // third step: load/sotre execution, ALU execution, branch completion
                state = 4; // default next state
                if ((opcode == LW) | (opcode == SW))
                    ALUOut <= A + SignExtend; //                         A
                else if (opcode == R_Type)
                    case (IR[5:0])
                        32: ALUOut = A + B; // add operation
                        default: ALUOut = A; // other operations
                    endcase
                else if (opcode == BEQ) begin
                    PC <= (A == B) ? ALUOut : PC; //                     B
                    state = 1;
                end
                else if (opcode == J)
                    PC <= {PC[31:28], IR[25:0], 2'b00}; //               C
                    state = 1;
                end
            end

            4: begin
                if (opcode == R_Type) begin // ALU Operation
                    Regs[IR[15:11]] <= ALUOut; //                        D
                    state = 1;
                end
                else if (opcode == LW) begin // load instruction
                    MDR <= Memory[ALUOut>>2]; // read the memory
                    state = 5; // next state
                end
                else if (opcode == SW) begin
                    Memory[ALUOut>>2] <= B; // write the memory
                    state = 1; // return to state 1
                end
            end

            5: begin // LW instruction
                Regs[IR[20:16]] <= MDR; //                               E
                state = 1;
            end // complete an LW instruction
        endcase
    end
endmodule

EEE305 2013-14

Question 1

1. A task always has to define I/O False
2. Port order doesn't matter when using port name instantiations True
3. output is a keyword when defining a function False
4. Non-blocking assignments are used when referring combinational logic False
5. A scalar wire is the default data type in Verilog True
6. The integer data type is unsigned False
7. In the statement assign a = b both a and b have to be reg data type False
8. (4'b00x0 == 4'b0x00) would give the result: 1'bx True
9. (4'b1100 | 4'b0000) would give the result: 4'b1111 False
10. (4'b1100 || 4'b0000) would give the result: 4'b1111 False

Question 2

1. 1BD命名格式错误
2. assign赋值的变量不能是reg
3. module后面括号的内容必须全部定义为port
4. always块中赋值的变量必须为reg，必须不能为wire
5. andgate使用错误

Question 3

module question3(A, B, C, D, E, F, G, H, I, J, K, L, SEL1, SEL2, CLK, RESET, Q1, Q2, Q3, Q4);
    input A, B, C, D, E, F, G, H, I, J, K, L, SEL1, SEL2, CLK, RESET;
    output reg Q1, Q2, Q3, Q4;
    wire D1, D2, D3, D4;
    initial begin
        Q1 = 0;
        Q2 = 0;
        Q3 = 0;
        Q4 = 0;
    end
    assign D1 = (A & B) ^ C ^ D,
           D2 = SEL1 ? D : (E | F),
           D3 = SEL2 ? I : (G & H),
           D4 = (~(J & K)) ~^ L;
    always @(posedge CLK) begin
        if (reset) begin
            Q1 = 0;
            Q2 = 0;
            Q3 = 0;
            Q4 = 0;
        end
        else begin
            Q1 = D1;
            Q2 = D2;
            Q3 = D3;
            Q4 = D4;
        end
    end
endmodule

Question 4

module question4(data, clock, reset, count);
    input data, clock, reset;
    output reg [6:0] count; // max = 128 > 100
    integer cycle;
    reg [3:0] value;
    initial begin
        count = 0;
        value = 4'b0000; //'
    end
    always @(posedge clock) begin
        if (!reset) begin
            cycle = 0;
            count = 0;
            value = 0;
        end
        else begin
            cycle = cycle + 1;
            if (cycle > 100) begin
                cycle = 0;
                count = 0;
                value = 0;
            end
            else begin
                value << 1;
                value[0] = data;
                if (value == 11) begin // 11(10) = 1011(2)
                    count = count + 1;
                end
            end
        end
    end
endmodule

Question 5

Moore

module question5(clock, resetn, w, z);
    input clock, resetn, w;
    output z;
    reg [1:0] y;
    parameter [1:0] S0 = 0, S1 = 1, S2 = 2; // 00 01 10
    always @(posedge clock or negedge reset) begin
        if (resetn == 0) y <= S0;
        else begin
            case (y)
                S0: if (w == 0) y <= S0;
                    else y <= S1;
                S1: if (w == 0) y <= S1;
                    else y <= S2;
                S2: y <= S0;
                default: y <= 2'bxx; // 'x会自动向左填充
            endcase
        end
    end
    assign z = (y == S1 || y == S2);
endmodule

EEE305 2012-13

Question 2

1. Verilog is case sensitive True
2. Verilog synthesizers treat the white space ' ' and carriage returns differently False
3. beginmodule and endmodule are reserved words in Verilog False
4. 2'b1x == 2'b1x has a true return value False
5. The semantics of an & operator depends on the number of operands True
6. An if statement must always be inside of an always block False
7. Verilog permits module ports to be unconnected True
8. The use of the initial keyword is to model circuit behaviour at time 0 and possibly beyond False
9. The left argument of a statement in an initial or always block may be a wire False
10. It is NOT necessary for a task to have inputs and outputs True

Question 3

module test(W, Y);
    input [7:0] W;
    output reg [2:0] Y;
    always @(W)
        case (W)
            8'b00000001: Y = 3'b000;
            8'b00000010: Y = 3'b001;
            8'b00000100: Y = 3'b010;
            8'b00001000: Y = 3'b011;
            8'b00010000: Y = 3'b100;
            8'b00100000: Y = 3'b101;
            8'b01000000: Y = 3'b110;
            8'b10000000: Y = 3'b111;
            default: Y = 3'bxxx;
        endcase
endmodule

(b)

module test(W, Y);
    input [7:0] W;
    output reg [2:0] Y;
    always @(W)
        case (W)
            8'b00000001: Y = 3'b000;
            8'b0000001x: Y = 3'b001;
            8'b000001xx: Y = 3'b010;
            8'b00001xxx: Y = 3'b011;
            8'b0001xxxx: Y = 3'b100;
            8'b001xxxxx: Y = 3'b101;
            8'b01xxxxxx: Y = 3'b110;
            8'b1xxxxxxx: Y = 3'b111;
            default: Y = 3'bxxx;
        endcase
endmodule

(c)

module test(W, Y);
    input [7:0] W;
    wire [7:0] data;
    reg [3:0] count = 0;
    output reg [2:0] Y;
    always @(W) begin
        Y = 7;
        for (count = 0; count < 8; count = count + 1)
            if (!(data && 8'b10000000)) begin
                data << 1;
                count = count + 1;
                Y = Y - 1;
            end
            else count = 8;
        end
        if (count == 8) Y = 3'bxxx;
    end
endmodule

EEE304 2013-14

Question 2

int x[20], i;
for i = 0 to 19
if x[i] < 17
    x[i] = 18;

Loop: sll $t1, $s1, 2
add $t1, $t1, $t0
lw $t0, 0($t1)
beq $s1, 20, Exit
addi $1, $1, 1
slti $t2, $t0, 17
beq $t2, 1, Do
j Loop
addi $t2, $zero, 18
Do: sw $t2, 0($t0)
j Loop
Exit: ...